Implementation of face recognition algorithm on field programmable gate array (FPGA)

Abstract

© 2019 World Scientific Publishing Company. The aim of this study is to implement an algorithm for face recognition, based on fast fourier transform (FFT), on the field programmable gate array (FPGA) chip. Implemented program included the initialization process of two single-IP-core ROM blocks, each with an image of a human face, which are sent to the real components of two-channel IP CoreFFT block. The result of classification could be displayed in the form of either a word yes or no on the seven-segment display or the information about the reference to the folder with the found match face. Due to the lack of memory on the chip, the results are discussed based on the results obtained by the simulation, whilst the implemented part of the system included displaying images on VGA monitor and result of the algorithm shown on seven-segment display or realized as a software solution in Matlab. The results show 79% accuracy and the advantage of presented system lies in the possibility of working with images in real time. The results obtained in this study can be a good starting point in the implementation of complex algorithms for face recognition using all the benefits that FPGAs offer.