A Design Generator of Parametrizable and Runtime Configurable Constant False Alarm Rate Processors

Abstract

Constant false alarm rate (CFAR) algorithms are widely used in radar signal processing for object detection in cluttered and noisy environments and their fast hardware implementation is required in many of the real time applications. For that purpose, a parametrizable and runtime reconfigurable generator of CFAR detectors, featuring fully streaming I/O data interface, is captured inside Chisel hardware design language. Generator provides up to seven different CFAR algorithms available to choose from in compile time and throughout runtime configurability. Besides the algorithm choice, a wide range of settings, such as I/O data type and bit-widths, reference and guard window sizes, linear or logarithmic processing modes, edge handling methods, as well as some implementation specific parameters, are provided, hence enabling quick and efficient design space exploration. Several generator instances are tested and verified on a commercially-available FPGA board in conjunction with off-the-shelf radar transceivers thus proving that instances from the proposed peak detector generator can be effectively used whenever low latency processing performance is mandatory.