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DC Field | Value | Language |
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dc.rights.license | restrictedAccess | - |
dc.contributor.author | Milovanović, Vladimir | - |
dc.contributor.author | Petrović, Marija | - |
dc.date.accessioned | 2021-04-20T16:45:55Z | - |
dc.date.available | 2021-04-20T16:45:55Z | - |
dc.date.issued | 2019 | - |
dc.identifier.uri | https://scidar.kg.ac.rs/handle/123456789/10823 | - |
dc.description.abstract | © 2019 IEEE. A configurable fast Fourier transform (FFT) engines and their inverse counterparts are indispensable in modern wireless communication and radar systems. The FFT processors are usually customized per use case. Therefore, a design generator of single-path delay feedback type of an FFT processor, that permits continuous input and output data streaming has been captured inside Chisel hardware construction language. It supports a wide range of parameter settings, like input data and twiddle factor widths, FFT sizes and number of stages, three radices, different scaling and rounding methods after each butterfly or dragonfly stage, among others, thus enabling an agile design space exploration. A comparison with commercially available FFTs which were specifically tailored for the particular FPGA platforms proves that FFT generator instances can be both performance-And resource-competitive with state of the art designs. | - |
dc.rights | info:eu-repo/semantics/restrictedAccess | - |
dc.source | 2019 IEEE 31st International Conference on Microelectronics, MIEL 2019 - Proceedings | - |
dc.title | A Highly parametrizable chisel hcl generator of single-path delay feedback fft processors | - |
dc.type | conferenceObject | - |
dc.identifier.doi | 10.1109/MIEL.2019.8889581 | - |
dc.identifier.scopus | 2-s2.0-85075369105 | - |
Appears in Collections: | Faculty of Engineering, Kragujevac |
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PaperMissing.pdf Restricted Access | 29.86 kB | Adobe PDF | ![]() View/Open |
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