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https://scidar.kg.ac.rs/handle/123456789/11364Full metadata record
| DC Field | Value | Language |
|---|---|---|
| dc.rights.license | restrictedAccess | - |
| dc.contributor.author | Papadopoulou A. | - |
| dc.contributor.author | Milovanović, Vladimir | - |
| dc.contributor.author | Nikolić B. | - |
| dc.date.accessioned | 2021-04-20T18:10:11Z | - |
| dc.date.available | 2021-04-20T18:10:11Z | - |
| dc.date.issued | 2017 | - |
| dc.identifier.uri | https://scidar.kg.ac.rs/handle/123456789/11364 | - |
| dc.description.abstract | © 2017 IEEE. A dual strong-arm (DSA) comparator is designed targeting at low-voltage operation in deeply-scaled technologies. The addition of a second regenerative latch helps reduce both offset sensitivity and offset while maintaining comparable or better performance as a conventional double-tail latch across a wide range of voltages. A large comparator offset measurement array is fabricated in a 28nm FDSOI process. The DSA offset is measured to be 8.5mV across 6 dies, approximately 30% lower than the conventional topology at iso-area and iso-capacitance conditions. It is also shown to scale well with supply and commonmode voltage, achieving up to 65% lower offset across the voltage range. | - |
| dc.rights | info:eu-repo/semantics/restrictedAccess | - |
| dc.source | 2017 IEEE Asian Solid-State Circuits Conference, A-SSCC 2017 - Proceedings | - |
| dc.title | A low-voltage low-offset dual strong-arm latch comparator | - |
| dc.type | conferenceObject | - |
| dc.identifier.doi | 10.1109/ASSCC.2017.8240271 | - |
| dc.identifier.scopus | 2-s2.0-85045725110 | - |
| Appears in Collections: | Faculty of Engineering, Kragujevac | |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| PaperMissing.pdf Restricted Access | 29.86 kB | Adobe PDF | ![]() View/Open |
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