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https://scidar.kg.ac.rs/handle/123456789/15883
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DC Field | Value | Language |
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dc.contributor.author | Krcum D. | - |
dc.contributor.author | Glavonjic D. | - |
dc.contributor.author | Mihajlović V. | - |
dc.contributor.author | Saranovac, Lazar | - |
dc.contributor.author | Milovanović, Vladimir | - |
dc.contributor.author | Milosavljević, Ivan | - |
dc.date.accessioned | 2023-02-08T16:00:41Z | - |
dc.date.available | 2023-02-08T16:00:41Z | - |
dc.date.issued | 2022 | - |
dc.identifier.issn | 0020-7217 | - |
dc.identifier.uri | https://scidar.kg.ac.rs/handle/123456789/15883 | - |
dc.description.abstract | A fully integrated 2-transmitter–4-receiver (2TX–4RX) multiple-input multiple-output (MIMO) radar front-end in the 57–64-GHz band for short-range applications is presented in this paper. The proposed architecture with 8 elements within a one-dimensional virtual array enables theoretical angular resolution down to (Formula presented.). The TX chains operate in time-division multiplexing (TDM) mode, and each delivers 12 dBm of saturated output power with output-referred 1-dB compression point (OP1dB) larger than 5 dBm over 7-GHz bandwidth. The millimeter-wave (mm-wave) part of the RX chains has a noise figure lower than 13 dB, and a conversion gain of 17 dB in the 60-GHz unlicensed band. The receiver chain shows a maximum conversion gain of 77 dB, while achieving an input-referred 1-dB compression point (IP1dB) greater than–12.5 dBm, including baseband circuitry. The programmable baseband processing chain with 60-dB gain allows beat frequency selection in the frequency range from 100 kHz up to 1.3 MHz. Linear chirps are synthesized using a fractional-N phase-locked loop (PLL) with a fundamental voltage-controlled oscillator (VCO). The integrated system includes a programmable multiplying delay-locked loop (MDLL) which scales-up external high purity 40-MHz frequency reference to a referent 240-MHz clock used in the frequency-modulated continuous-wave (FMCW) synthesizer. The front-end is implemented in a 130-nm SiGe:C BiCMOS process. The chip occupies an area of 12 mm2 including pads and consumes 930 mW, combined from 1.2-V and 3.3-V supplies. | - |
dc.rights | info:eu-repo/semantics/restrictedAccess | - |
dc.source | International Journal of Electronics | - |
dc.title | A fully integrated 2TX–4RX 60-GHz FMCW radar transceiver for short-range applications | - |
dc.type | article | - |
dc.identifier.doi | 10.1080/00207217.2022.2062793 | - |
dc.identifier.scopus | 2-s2.0-85129816640 | - |
Appears in Collections: | Faculty of Engineering, Kragujevac |
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PaperMissing.pdf Restricted Access | 29.86 kB | Adobe PDF | ![]() View/Open |
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