An Eight-Core 1.44-GHz RISC-V Vector Processor in 16-nm FinFET

Abstract

This work presents a RISC-V system-on-chip (SoC) with eight application cores containing programmable-precision vector accelerators. The SoC is built by using a generator-based design methodology, which enables the integration of open-source and project-specific building blocks to develop differentiated functionality. The digital component generators use Chisel, the analog component generators use the Berkeley Analog Generator (BAG), and the physical design flow is implemented with Hammer. The chip totals 125 M gates and is implemented in a 16-nm finFET process. The vector accelerator achieves peak energy efficiency per task of 209 half-precision, 92 single-precision, and 56 double-precision GFLOPs/W for a matrix multiplication kernel at 0.55 V and 339 MHz.