Please use this identifier to cite or link to this item: https://scidar.kg.ac.rs/handle/123456789/14007
Title: A Chisel Generator of Parameterizable and Runtime Reconfigurable Linear Insertion Streaming Sorters
Authors: Petrovic M.
Milovanović, Vesna
Journal: Proceedings of the International Conference on Microelectronics, ICM
Issue Date: 12-Sep-2021
Abstract: Fully streaming linear sorters with their rather simple and low-cost hardware architecture are widely used as the fundamental building blocks in many digital signal processing applications that require sorting operations and continuous data streaming interfaces. Therefore, a parameterizable and runtime reconfigurable generator of fully streaming sorters based on an insertion sort algorithm are captured inside Chisel hardware design language in order to enable fast and efficient agile design space exploration. A broad range of parameter settings are supported with the proposed generator, such as sorting data type and data width in number of bits, discarding element position inside the sorting array, compile and runtime reconfigurable sorter depth, sorting direction, control and status register access bus, etc. Various generator instances have been mapped onto a commercially available FPGA platform, tested and mutually compared. It is proven that such a generator can yield resource and performance competitive sorter designs.
URI: https://scidar.kg.ac.rs/handle/123456789/14007
Type: conferenceObject
DOI: 10.1109/MIEL52794.2021.9569153
SCOPUS: 85118424351
Appears in Collections:University Library, Kragujevac

Page views(s)

42

Downloads(s)

2

Files in This Item:
File Description SizeFormat 
PaperMissing.pdf
  Restricted Access
29.86 kBAdobe PDFThumbnail
View/Open


Items in SCIDAR are protected by copyright, with all rights reserved, unless otherwise indicated.